Looking into the MIO pins on the Zynq. We can have PS periphs access MIO pins (top-left pic), or optionally go to the PL via EMIO (top-right). However, it's not clear to me if we can configure things such that the PL controls selective PS_MIO pins as in the bottom pic?

This document describes how to configure MIO pins as General Purpose Input/Output pins (GPIOs). The “Configuring the GIC for GPIO Interrupts” document describes how to use interrupts with the GPIO inputs. Several registers are are used to configre the MIO pins.

The MIO also contains the configuration settings that determine how the Zynq SoC boots. The MIO connects to the PS (processor system) side of the Zynq SoC. It connects to 54 pins on Zynq devices (note that the Zynq-7010 SoC in the CLG225 package has 32 MIO pins), which are used for the following:

Mar 11, 2025 · Routing a signal through an MIO can be a two-step process. The I/O buffer attributes are listed in Output Buffer Control Registers. The steps to configure the input for LPD MIO pin 18 include: Select the MIO (PMC or LPD) using LPD_MIO_Sel (0: PMC MIO). Route the signal through the MIO using the MIO_PIN_18 register. Disable the output driver.

Dec 20, 2018 · In Zynq 7000, PS can use GPIO to monitor or control the signals in PL and in external world via EMIO and MIO respectively. The GPIO peripheral provides a software with observation and control of up to 54 device pins via the MIO module.

This short tutorial will walk you through on how you can configure ZYNQ7 processing system so that MIO pins would be used for certain peripherals, such as SPI,I2C, and UART. Open up ZYNQ7 Processing System by double clicking on the IP block. Figure 1. Open ZYNQ7 Processing System. Click on Peripheral MIO Pins.

The MIO pins go directly to to processor system from package pins, as defined by the IO mux settings which are part of the FSBL. The EMIO pins go from the processoer system, to the programmable logic, and may be used however you wish.

The MIO pins and any restrictions based on device versions are shown in the MIO table in section MIO-at-a-Glance Table . Table 19-4: UART MIO Pins and EMIO Signals UART Interface Signal Default Controller Input Value MIO Pins EMIO Signals Nu...

Jun 30, 2023 · The MIO-at-a-Glance table, the interface routing table, and these pin assignment considerations are helpful when doing pin planning. Interface Frequencies: The clocking frequency for an interface usually depends on device speed grade and whether the interface is routed via MIO or EMIO.

Oct 24, 2014 · For the peripherals (UART, SPI, I2C, CAN, USB, ...) that are part of Zynq micro-controller (part of PS) you can select if peripherals pins are MIO or EMIO. MIO pins are predefined, you can pick pins from predefined sets of possible pin …