Apr 18, 2018 · It is common for devices like FPGAs to use weak pull-ups on all pins until configuration completes. Depending on the FPGA, it may be possible to enable the pull-ups after configuration on a pin by pin basis, usually by specifying this in constraints files.

Jul 4, 2015 · After configuration, a pin may be set to pull up, or pull down, or to remain floating (effectively tri-state) or be driven high or driven low, depending on the IO standard chosen. It does no harm to have pins float.

Sep 11, 2023 · i/o和时钟规划是定义和分析fpga和印刷电路板（pcb）之间连接的过程，并将各种互连信号分配给fpga器件的物理管脚，正确的规划i/o端口和时钟分配会提高fpga系统性能、减少设计迭代和缩短计开发时间。本文主要介绍时钟及i/o规划的各个阶段及流程要点。

Both pull-up and pull-down resistors on all configuration pins, even with HSWAP tied low (via a resistor). This is a lot of extra resistors and seems to defeat the purpose of HSWAP all together.

We are using Xilinx's Virtex 4 FPGA (XC4VLX60-FF668) on our board. I am trying to configure the PADs with PULLUP's, for resetb inputs. Can anyone please explain me how these Xilinx's internal pullup/down's work (Pullup/down resistors)?

The pull up / down 'resistors' on the chip are current mirrors, not real resistors. They are not intended to pull up as you are thinking of them, they are designed for floating lines, a hang over form the old tri state bus days.

Jul 27, 2016 · It seems is possible to activate weak pull up for an I/O in quartus. But there is no information on how to activate it. Any hints? In the Assignment Editor, set the weak pull-up assignment to ON to enable the on-chip pull-up resistor for the pin.

May 25, 2015 · If you are referring to reserving unused IO pin to pull up/down internal, you could do the following: 1. Open up QII pin planner 2. Right click on a IO pin 3. Look for Reserve 4. Then select if you want the reserved pin to be connected to VCC or GND. You can then verify the compilation through .pin file or Fitter report. 05-25-2015 11:21 AM.

Nov 22, 2021 · Doing FPGA lobotomy for a thing that simple microcontroller can do with 3 instructions or less. Adding support for post-configuration control over pull-up and pull-down resistors would just add more complexity to an already complex (from a configuration standpoint) device, for little gain.

Sep 24, 2024 · When calculating a pull-up/pull-down resistor for any logic type you normally consider the DC operating conditions i.e. leakage current of the gate input and voltage threshold required. You also need to consider the transition time from e.g. low to high.