All "14 nm" nodes use FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology.

Intel has reduced our thermal design power from 18W in 2010 to 11.5W in 2013 to 4.5W with the new Intel Core M processor. That’s a 4X reduction over 4 years and a 60% reduction year over year.

Mar 19, 2025 · IBM's HP 14nm CMOS process features a FinFET architecture on an SOI substrate. The use of SOI with FinFET gives IBM a number of unique advantages such as lower parasitic capacitance at the base of the fin as well as simplifies patterning of the active fins and minimizes their variability such as height and thickness.

The FinFET technology is continuously progressing toward 14nm node on SOI and bulk substrate with good compatibility with planar CMOS and driving CMOS scaling and Moore's law for low-power/SOC and future Internet-of-Things (IOT) applications.

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.

In this work, we first design and evaluate the 14nm Finfet based TR-L M3D ICs using silicon validated 14nm Finfet process design kit (PDK). We design compact 3D standard cells where the pull-up and pull-down network are redesigned by fully using 3D routing spaces and considering Finfet design rules.

This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively.

Dec 6, 2017 · Abstract: This paper describes the features and performance of an analog and RF device technology development on a 14-nm logic FinFET platform. An optimized single-side gate contact RF device layout shows a F t /F max of 314/180 GHz and 285/140 GHz for N and PFinFET device, respectively.

This paper describes the implementation of a high performance FinFET-based 14-nm CMOS Technology in Microwind. New concepts related to the design of FinFET and design for manufacturing

Jan 1, 2015 · In this chapter, we provide the design guidelines for bulk FinFETs at the 14 nm node, and compare bulk and SOI FinFETs in terms of scalability, parasitic capacitance, and heat dissipation. Decrease of the drain current by parasitic resistance in the source (S) and drain (D) regions is also addressed.