Home - VLSI Verify
Our goal is to share in-depth knowledge of VLSI design and Verification to bridge the gap between students and industries. We provide well-structured easy to understand lessons along with one-click executable examples on the EDA playground.
ASIC Verification Flow - VLSI Verify
ASIC Verification Flow includes phases like verification architecture, verification plan, testplan, testbench development, testcase coding, simulation, etc
Verification process and Testbench - VLSI Verify
The verification process allows verification engineers in finding bugs, checking for RTL correctness based on the design specification.
UVM - VLSI Verify
UVM is based on Open Verification Methodology (OVM) and Verification Methodology Manual (VVM). The UVM API (Application Programming Interface) provides standardization for integration, creation of verification components. The API also scales from block-level to system-level verification environment. Advantages of UVM based testbench
Functional Coverage - VLSI Verify
Verification engineers aim to achieve 100% code coverage. There are industry tools available that show covered and missing code in code coverage.
System Verilog - VLSI Verify
SystemVerilog is commonly used in the semiconductor. It is a hardware description and hardware verification language used to model, design, simulate testbench. SystemVerilog is based on Verilog and some extensions. It is standardized as IEEE 1800.
SystemVerilog Assertions - VLSI Verify
An assertion also provides function coverage that makes sure a certain design specification is covered in the verification. The methodology that uses assertions is commonly known as “Assertion Based Verification” (ABV).
IP vs Sub-System Vs SoC Verification - VLSI Verify
Are you confused with the terminologies: what are IP, sub-system, and SoC verification? In this article, our focus is to understand the verification domain, exploring its key aspects, and associated job roles. The front-end verification is mainly categorized into three: IP verification; Sub-System verification; SoC verification
Interview Questions - VLSI Verify
We tried to provide the most commonly asked interview question in the Verification domain in three categories – Basic, Intermediate, and Difficult level questions for Verilog, SystemVerilog languages, and UVM methodology.
RAL Model - VLSI Verify
RAL model provides a set of methods and rules that make verification engineer job easy, The register abstraction layer provides standard base class libraries. It is used to create a memory-mapped model for registers in DUT using an object-oriented model.