We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first appr.

SiGe shows enormous potential for bringing all the benefits of Si semiconductor device technology firmly into the high frequency world of analog electronics. This report compares the …

One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined …

Jan 17, 2019 · Several methods have been proposed to improve uniformity of SiGe growth but none of these could effectively eliminate the layout dependency of the SEG. In this study, the …

Feb 1, 2017 · In this study, we investigate the layout effects induced by the SiGe channel in the pMOSFETs of the 14 nm UTBB-FDSOI technology. The threshold voltage and the linear drain …

Abstract: A D-Band SiGe HBT low-noise amplifier (LNA) is presented in IHP's 0.13-μm SiGe BiCMOS technology. The proposed 3 stage cascode common emitter architecture provides a …

Advances in silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) technologies resulted in an impressive increase in high-frequency performance during the last decade …

Modern SiGe BiCMOS technology has significant potential for high-speed, high-power applications in the sub-THz range, where improvements are made continuously with the help …

integrated circuit (IC) chips containing various silicon-germanium (SiGe) APDs with different sizes, structures, and geometries were designed, laid out, and fabricated using the …

schematic of a basic strained Si heterostructure. The three basic elements are the bulk Si substrate, the epitaxial SiGe buffer layer, which creates a larger lattice constant, and the …