Fig. 2. TLP characteristics of four PNP-based ESD protection structures optimized for high voltage I/OS. The obtained result is already satisfactory for protecting a 50V I/O but not enough for protecting an 80V one since it requires to stack two protections thus inducing a significant R ON degradation. We then studied a way to improve the R

View of the improved PNP ESD protection (top) and TLP characteristics of two optimized PNP-diode structures (30V and 60V clamping voltages) and of a standalone optimized PNP (bottom). This...

We demonstrate a PNP electrostatic discharge (ESD) protection device with adjustable trigger and holding voltage, proposed and verified in a 0.18- μm BCD process for 8–65-V applications.

This paper presents a comprehensive physical model for PNP based ESD protection device. The model includes all major physical effects of device during ESD operation, which enables the model to capture the DC, AC and dynamic effects like …

The transient response of the proposed Bi-PNP device under fast ESD stress was investigated by very fast TLP (vf-TLP) and TLP measurement. In addition, the empirical correlations of the It2 on the HBM and IEC 61000-4-2 failure levels were esti-mated.

Aug 18, 2022 · The transient response of the proposed Bi-PNP device under fast ESD stress was investigated by very fast TLP (vf-TLP) and TLP measurement. In addition, the empirical correlations of the It2 on the HBM and IEC 61000-4-2 failure levels were estimated.

Aug 1, 2021 · The TLP characterization results of the lateral parasitic PNP with different geometry parameters match well with the simulation results, while the scalability of the failure current is analyzed in the experiment part.

Sep 1, 2020 · Aiming at protecting IO pins operating in the 0–1.8 V range and 2.2 V–6.0 V ESD design widow, a novel dynamic substrate GGNMOS with imbedded PNP transistor was proposed and verified in a 0.18 μm salicided CMOS technology. The TLP, vf-TLP and TCAD simulation was conducted to characterize its ESD properties.

Aug 1, 2021 · The TLP characterization results demonstrate that the triggering voltage V t1 is strongly influenced by the base region (i.e., base width), and on-resistance R ON is mainly affected by the collector region (i.e., collector width) for the finger-type parasitic PNP.

Aug 24, 2022 · With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed.