Jan 19, 2009 · Forward error correction (FEC) is a technique for handling lossy storage devices or transmission channels. A FEC code takes k blocks of data and produces an additional m blocks of encoding information, such that any set of k of the blocks (out of the k+m total) is sufficient to recover the original data.

TurboFEC is an implementation of LTE forward error correction encoders and decoders. Included are convolutional codes, turbo codes, and associated rate matching units that handle block interleaving, bit selection, and pruning.

This is a set of functions for forward error correction (FEC). The code uses Agner Fog's vector class library (https://github.com/vectorclass - at a minimum get the "version2-master" files). …

SIMD SUPPORT This package automatically makes use of various SIMD (Single Instruction stream, Multiple Data stream) instruction sets, when available: MMX, SSE and SSE2 on the IA-32 (Intel) architecture, and Altivec on the PowerPC G4 and G5 used by Power Macintoshes.

AFF3CT is an Open-source software (MIT license) dedicated to the Forward Error Correction (FEC or channel coding) simulations. It is written in C++11 and it supports a large range of codes: from the well-spread Turbo codes to the new Polar codes including the …

Aug 7, 2007 · This library package provides several forward error correction (FEC) decoders and accelerated primitives useful in digital signal processing (DSP). Except for the Reed-Solomon codecs, these functions take full advantage of the MMX, SSE and SSE2 SIMD instruction sets on Intel/AMD IA-32 processors and the Altivec/VMX/Velocity Engine SIMD ...

This package provides a set of functions that implement several popular forward error correction (FEC) algorithms and several low-level routines useful in modems implemented with digital signal processing (DSP).

Jul 20, 2023 · This library package provides several forward error correction FEC decoders and accelerated primitives useful in digital signal processing DSP. Except for the Reed-Solomon codecs, these functions take full advantage of the MMX, SSE and SSE2 SIMD instruction sets on Intel/AMD IA-32 processors and the Altivec/VMX/Velocity Engine SIMD instruction ...

Jan 10, 2024 · This library package provides several forward error correction (FEC) decoders and accelerated primitives useful in digital signal processing (DSP). Except for the Reed-Solomon codecs, these functions take full advantage of the MMX, SSE and SSE2 SIMD instruction sets on Intel/AMD IA-32 processors and the Altivec/VMX/Velocity Engine SIMD ...

Jan 22, 2021 · All Steinwurf’s ECC/FEC algorithms utilize SIMD acceleration with run-time detection of the CPU capabilities. This means the same binary can run on multiple different CPUs and automatically utilize the fastest SIMD acceleration available.