A Short Review of Through-Silicon via (TSV) Interconnects ... - MDPI
Jul 18, 2023 · Since the year 2000, copper (Cu) plating in deep via holes has emerged as the primary technology for filling high aspect ratio TSVs [6, 7, 8]. The goal of electroplating is low stress, free of holes and voids during TSV fabrication [9].
Correlation between Cu microstructure and TSV Cu pumping
Abstract: Cu pumping is the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures during back-end of line (BEOL) processing. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread.
Through Silicon Via Copper - DuPont
Through silicon vias (TSVs) are vertical electrical interconnects formed using wafer etch processes and filled with either Cu or tungsten. First introduced in compound semiconductor applications, TSVs are also used in MEMS devices and CMOS image sensors, to create 3D memory stacks, and 2.5D interposer architectures, driven by high-performance ...
Dynamic through-silicon-via filling process using copper ... - Nature
Apr 19, 2017 · In this study, we demonstrate the TSV dynamic filling process through staged electrodeposition experiments at different current densities. The optimum current density to achieve defect-free...
Low Stress TSV Arrays for High-Density Interconnection
Jul 1, 2024 · Li et al. [16] fabricated a ring-shaped copper TSV (Cu–TSV) with an aspect ratio of 10:1 and filled the sidewall of the TSV with Cu metal with a thickness of 2 μm by sputtering, which can achieve lower thermal stress than the solid Cu–TSV.
Simulation and fabrication of two Cu TSV electroplating methods …
Dec 1, 2013 · Three-dimensional (3-D) integration and packaging with through silicon via (TSV) is an emerging trend for overcoming the limitation of integration scale in Micro-electro-mechanical systems (MEMS) packaging. It is helpful for the realization of high density and reliability of micro-devices and sensors.
Microstructure investigation of TSV copper film - IEEE Xplore
In this study, physical vapor deposition (PVD) and electroplated (ECP) Cu TSV microstructure evolution with Ti and Ta barrier after thermal annealing was investigated. As deposited PVD Cu grain showed a preferred orientation on (111) and transformed into (001) after annealing.
Cu pumping in TSVs: Effect of pre-CMP thermal budget
Sep 1, 2011 · When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV.
Effect of annealling process on microstructure of Cu-TSV
Copper filled in through silicon via (Cu-TSV) technology with good electrical performance and high reliability, is a new type of 3D packaging technology. Cu-TSV has been widely used in integrated circuit technology due to its excellent interconnection performance.
Correlation between Cu Microstructure and TSV Cu Pumping
May 27, 2014 · This paper describes a clear correlation between Cu pumping and TSV Cu microstructure based on the grain size at the top of 5 × 50 μm TSV, disregarding twin boundaries.