Core Manager and Power Control (CPU PIK) registers The core manager and power control registers enable configuration of reset values and clock settings for subsystems. The following table lists the fully configured power control register summary.

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The Power Policy Unit (PPU) power control registers are defined inside Arm® Power Policy Unit Architecture Specification, version 1.1. The core manager and power control registers enable configuration of reset values and clock settings for subsystems.

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The System PIK registers enable configuration of clock settings for the system Power Integration Kit. The System PIK is only mapped into the System Control Processor (SCP) memory map. For more information, see SCP memory map. The System PIK occupies a 64KB which is split into 4KB blocks as shown in the following table: Table 1.

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