As of the Xilinx Vivado 2020.1 release, the MIPI DSI (display serial interface) and CSI (camera serial interface) IP blocks are now bundled with the IDE to be used freely with Xilinx FPGAs.

For developers on Xilinx FPGAs they have extended the offer of those two processor cores at zero cost through their DesignStart Programme. It’s free-as-in-beer rather than something that will ...

AMD said it has completed its $49 billion acquisition of Xilinx to create the “industry’s high-performance and adaptive computing leader,” marking the largest chip deal in history.

CRN dives into the details of the Xilinx deal and what it could mean for the data center and telecom markets, among other things. ‘It’s Not M&A For M&A’s Sake’ In a little over a month ...

SAN JOSE, Calif. -- Aug. 21, 2019 -- Xilinx, Inc. (NASDAQ: XLNX), the leader in adaptive and intelligent computing, today announced the expansion of its 16 nanometer (nm) Virtex® UltraScale+™ family ...

This SATA Host IP core has been certified for Serial ATA Revision 3.0 compliance on a Xilinx Virtex-6 FPGA by the UNH IOL SATA Consortium in May 2010. ASICS World Services provides a broad line of ...