TSMC will discuss its development of a monolithic CFET inverter on a 48nm gate pitch, equivalent to a 5nm process. The inverter features stacked n-type and p-type nanosheet transistors with ...

By way of example, TSMC's N3E node as used in the latest Apple chips has gate pitch of at minimum 45 nm and a metal pitch of ...

[1] 'Nanosheet-based complementary field-effect transistors (CFETs) at 48nm gate pitch, and middle dielectric isolation to enable CFET inner spacer formation and multi-Vt patterning', H. Mertens et al ...

Imec has developed a GaN MOSHEMT on silicon that achieves both record efficiency and output power for an enhancement-mode ...

MediaTek announced its first 3nm process chip last week, an unnamed flagship Dimensity SoC that is due to enter mass production in 2024. The news was big, as no other major mobile chip designer ...

Transistor timers and multivibrators were covered, ... The organ project awaits, but before then we have time for a couple more circuits to get used to varying the pitch of the oscillator.

In the mid-1990s, gate length started shrinking much faster than the half pitch. Then, in the 2000s, problems with power and waste heat saw progress in shrinking gate lengths slow down sharply.

A great Sony transistor story: in the 1960s Sony invented a very small transistor radio. So small it was portable! They wanted to emphasize how small it was so they decided to sell it in America ...

MediaTek just announced its first 3nm process chip, and Apple may also announce its own very soon. But what are these 3nm chips?