For the past 25 years, geometric scaling of silicon CMOS transistors has enabled not only an exponential increase in circuit integration density — Moore's Law — but also a corresponding enhancement in ...

Strained Silicon When the silicon is adhered to the silicon germanium, the silicon atoms are stretched. Advertisement. THIS DEFINITION IS FOR PERSONAL USE ONLY.

No. 2 chip maker AMD, which is researching strained silicon and other technologies with IBM, isn’t planning to sell microprocessors with a significant degree of strained silicon until 2005 or ...

Silicon Genesis Corporation (SiGen) announced today that it has successfully developed a new wafer-level strained substrate technology, called “Next-Generation Strain” or NGS. NGS features ...

The main method for making a wafer-scale strained silicon layer that is process independent and uniform is the creation of a virtual Si1-xGex substrate. Because the silicon germanium lattice is larger ...

Strained silicon--which will appear in Intel's Prescott chip next year--stretches the distances between the silicon atoms in transistors, the tiny on/off switches that form the basis of a chip.

Strained Silicon is gaining wide acceptance as the material of the future for semiconductors as evidenced by IBM’s announcement, Wolf said. AmberWave and its founder, MIT Professor Dr. Gene ...

Like their SOI cousins, strained-silicon chips built on insulator function at significantly higher speeds-as much as 30 percent more-than those built on strained silicon without the insulating layer.

Chip performance is being improved by pulling silicon atoms apart, and in some cases pushing them closer together. IBM, AMD claim a better way to strain silicon - CNET X ...

Standard strained silicon has so many dislocations and defects that strain measurements aren't accurate, so the research team starts with its own specially fabricated silicon nanomembranes.

As companies struggle to push strained silicon technology into the mainstream at the 90-nm process node for greater digital-circuit performance, new variations lurk at 65 nm ...

IBM and Advanced Micro Devices have devised a new way of straining silicon--a design technique that improves chip performance--they claim will be cheaper, faster and easier to implement. Called ...