As the era of multi-chiplet designs looms ... Now, the institute aims to collaborate with both SiP designers, who would use the new technology, and foundries, to prepare the technology for ...

JEDEC and OCP (Open Compute Project Foundation) announce new Chiplet Design Kits for EDA use covering four areas: Assembly, Substrate, Material and Test. Basically, they are a way for chiplet builders ...

A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel. “Universal ...

Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innovative multi-chiplet designs. This UCIe chiplet ...

AI hardware startup Axelera AI has unveiled its Titania AI inference chiplet. The company announced the hardware ... Multiple Titania chiplets will be packaged in a System-in-Package (SiP). “Our D-IMC ...

Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller is a high-bandwidth, low-power and low-latency ...

How it works: The Titania chiplet-based architecture will leverage the company ... Multiple Titania chiplets will be packaged in a System-in-Package (SiP). “This is an important milestone and ...